This invention relates to digital logic circuits and more particularly to an arbiter circuit of the kind employing cross-coupled NAND gates that overcomes the susceptibility of the NAND gates to become metastable, and effectively blocks the transmission of this condition until such time as the outputs are in one of two stable states.
An arbiter circuit is used in digital logic to (a) respond to a first one of two signals that may arrive at a slight difference in time, so as to give priority to such asynchronous signals on a first come first serve basis, and (b) in the case of signals that arrive at the same instant in time, make an arbitrary decision as to which of the two signals it will respond to first.
Arbiter circuits commonly employ a latch made up of two cross-coupled NAND gates. One of the problems frequently encountered in such arbiter circuits arises from a metastable condition of the cross-coupled NAND gates where the latch output is neither HIGH nor LOW but is in an intermediate state (metastable state). This condition is usually preceded by the production in the output of the latch of what is called a "rut" pulse. A rut pulse is characterized as a narrow, zero-going or positive-going pulse which is too narrow to be effective, but wide enough to be detected in the output bus. While the probability of a metastable state existing can be reduced or the duration of the metastable state can be reduced, it is extremely unlikely that this condition can be completely eliminated. Thus it becomes necessary to provide some means whereby the rut pulses, and/or the metastable levels, when they occur, can be blocked from reaching the succeeding logic devices.